Ultra high density flash memory

ABSTRACT

An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for four vertical floating gate transistors that have individual floating and control gates distributed on the four sides of the pillar. Mutually orthogonal first gate lines and second gate lines provide addressing of the control gates. First source/drain terminals are row addressable by interconnection lines disposed substantially parallel to the first gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the second gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F 2  is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F 2  is needed per bit of data.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. application Ser. No.09/866,938, filed May 29, 2001, which is a Divisional of U.S.application Ser. No. 09/035,304, filed Feb. 27, 1998, which is aDivisional of U.S. application Ser. No. 08/889,554, filed Jul. 8, 1997,now issued as U.S. Pat. No. 5,973,356, all of which are incorporatedherein by reference.

This application is related to U.S. Pat. No. 5,936,274, which disclosureis herein incorporated by reference.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to integrated circuits, andparticularly to floating gate transistor structures for use innonvolatile semiconductor memories such as in flash EEPROM memory cells.

BACKGROUND OF THE INVENTION

Electrically erasable and programmable read only memories (EEPROMs) arereprogrammable nonvolatile memories that are widely used in computersystems for storing data both when power is supplied or removed. Thetypical data storage element of an EEPROM is a floating gate transistor,which is a field-effect transistor (FET) having an electrically isolated(floating) gate that controls electrical conduction between source anddrain regions. Data is represented by charge stored on the floating gateand the resulting conductivity obtained between source and drainregions.

Increasing the storage capacity of EEPROM memories requires a reductionin the size of the floating gate transistors and other EEPROM componentsin order to increase the EEPROM's density. However, memory density istypically limited by a minimum lithographic feature size (F) that isimposed by lithographic processes used during fabrication. For example,the present generation of high density dynamic random access memories(DRAMS), which are capable of storing 256 Megabits of data, require anarea of 8F² per bit of data. There is a need in the art to provide evenhigher density memories in order to further increase storage capacity.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like numerals describe substantially similar componentsthroughout the several views.

FIG. 1 is a schematic/block diagram illustrating generally anarchitecture of one embodiment of a nonvolatile memory, according to theteachings of the invention, including an array having a plurality ofmemory cells.

FIG. 2 is a schematic diagram illustrating generally one embodiment ofan array of memory cells according to the teachings of the invention.

FIG. 3 is a perspective view illustrating generally one embodiment of aportion of an array of memory cells according to the teachings of theinvention.

FIG. 4 is a plan view from above of a working surface of a substrate,which illustrates one embodiment of one of a memory cell according tothe teachings of the invention.

FIGS. 5-20 illustrate generally various stages of one embodiment of amethod of forming an array of memory cells according to the teachings ofthe invention.

FIG. 21 is a perspective view of a structure dating from anotherembodiment of a method of forming the array of memory cells according tothe invention, using semiconductor-on-insulator (SOI) techniques.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof. and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that the embodiments may be combined, or that otherembodiments may be utilized and that structural, logical and electricalchanges may be made without departing from the scope of the presentinvention. In the following description, the terms wafer and substrateare interchangeably used to refer generally to any structure on whichintegrated circuits are formed, and also to such structures duringvarious stages of integrated circuit fabrication. Both terms includedoped and undoped semiconductors, epitaxial layers of a semiconductor ona supporting semiconductor or insulating material, combinations of suchlayers, as well as other such structures that are known in the art,including bulk semiconductor and semiconductor-on-insulator (SOI)substrates. In the drawings, like numerals describe substantiallysimilar components throughout the several views. The following detaileddescription is not to be taken in a limiting sense.

FIG. 1 is a schematic/block diagram illustrating generally anarchitecture of one embodiment of a memory 100 according to the presentinvention. In the embodiment of FIG. 1, memory 100 is a nonvolatileultra high density electrically erasable and programmable read onlymemory (EEPROM) allowing simultaneous erasure of multiple data bits,referred to as flash EEPROM. However, the invention can be applied toother semiconductor memory devices, such as static or dynamic randomaccess memories (SRAMs and DRAMS, respectively), synchronous randomaccess memories or other types of memories that include a matrix ofselectively addressable memory cells.

Memory 100 includes a memory cell array 105, having memory cells thereinthat include floating gate transistors, as described below. Y gatedecoder 110 provides a plurality of first gate lines, YG1, YG2, . . . ,YGN for addressing floating gate transistors in array 105, as describedbelow. X gate decoder 115 provides a plurality of second gate lines,XG1, XG2, . . . , XGN for addressing floating gate transistors in array105, as described below. Y source/drain decoder 120 provides a pluralityof first source/drain interconnection lines YS1, YS2, . . . , YSN, foraccessing first source/drain regions of the floating gate transistors inarray 105, as described below. In an embodiment in which commonlyconnected first source/drain interconnection lines YS1, YS2, . . . , YSNare used, Y source/drain decoder 120 may be omitted. X source/draindecoder 125 provides a plurality of data lines, XD1, XD2, . . . , XDNfor accessing second source/drain regions of the floating gatetransistors in array 105, as described below. X source/drain decoder 125also typically includes sense amplifiers and input/output (I/O)circuitry for reading, writing, and erasing data to and from array 105.In response to address signals A0-AN that are provided on address lines130 during read, write, and erase operations, address buffers 135control the operation of Y gate decoder 110, X gate decoder 115, Ysource/drain decoder 120, and X source/drain decoder 125. The addresssignals A0-AN are provided by a controller such as a microprocessor thatis fabricated separately or together with memory 100, or otherwiseprovided by any other suitable circuits. As described in detail below,the address signals A0-AN are decoded by Y gate decoder 110, X gatedecoder 115, Y source/drain decoder 120, and X source/drain decoder 125to perform reading, writing, and erasing operations on memory cells thatinclude a number of vertical floating gate field-effect transistors(FETs) formed on the sides of a semiconductor pillar on a substrate.

FIG. 2 is a schematic diagram illustrating generally one embodiment ofarray 105 in more detail. In FIG. 2, each memory cell 205 comprises fourfloating gate transistors 200, e.g. four field-effect transistors(FETS), each having an electrically isolated (floating) gate thatcontrols electrical conduction between source and drain regions. Thefloating gate transistors 200 are arranged in cells 205, such as cells205AA, 205BA, . . . , 205NA, in a first direction, e.g. in theY-direction of the first source/drain interconnection lines YS1, YS2, .. . , YSN, and in cells such as 205AA, 205AB . . . , 205AN in a seconddirection, e.g. in the X-direction of the data lines, XD1, XD2, . . . ,XDN. In the embodiment of FIG. 2, each cell 205 includes four floatinggate transistors 200 that share a common first source/drain region, suchas a source region coupled to one of the first source/draininterconnection lines YS1, YS2, . . . , YSN. The floating gatetransistors 200 of each cell 205 also share a common second source/drainregion, such as a drain region coupled to one of the data lines, XD1,XD2, . . . , XDN. Each cell 205 has first and second source/drainregions that are fabricated using a common semiconductor pillar on asubstrate, as explained below.

FIG. 3 is a perspective view illustrating generally one embodiment of aportion of array 105, including portions of two cells 205 of floatinggate transistors 200, such as illustrated in FIG. 2. In FIG. 3, thesubstantially identical cells 205 are illustrated by way of examplethrough cells 205AA and 205BA. Cells 205AA and 205BA each include asemiconductor pillar 300, initially of a first conductivity type such asP-silicon, fabricated upon a monolithic substrate 305. In oneembodiment, substrate 305 is a bulk semiconductor, such as P-silicon. Inanother embodiment, a semiconductor-on-insulator (SOI) substrate 305includes an insulating layer, such as silicon dioxide (SiO₂), asdescribed below.

Each pillar 300 includes a first source/drain region of a secondconductivity type, such as N+ silicon source region 310, formedproximally to a sub-micron dimensioned interface between pillar 300 andsubstrate 305. Each pillar 300 also includes a second source/drainregion of the second conductivity type, such as N+ silicon drain region315, that is distal to substrate 305, and separated from source region310 by a first conductivity type region, such as P-body region 320.

Each pillar 300 provides a source region 310, a drain region 315, and abody region 320 for the four floating gate transistors 200 of aparticular memory cell 205. In one embodiment, the physical dimensionsof each pillar 300 and the doping of P-body region 320 are bothsufficiently small to allow operation of the floating gate transistors200 that is characteristic of fully depleted body transistors. Firstsource/drain region interconnection line YS1 electrically interconnectsthe source region 310 of each pillar 300. of cells 205AA, 205BA, . . . ,205BN. In one embodiment, the first source/drain interconnection linesYS1, YS2, . . . , YSN, comprise a conductively doped semiconductor ofthe second conductivity type, such as N+ silicon, disposed at leastpartially within substrate 305. For example, dopants can beion-implanted or diffused into substrate 305 to form the firstsource/drain interconnection lines YS1, YS2, . . . , YSN. In anotherembodiment, the first source/drain interconnection lines YS1, YS2, . . ., YSN are formed above substrate 305. For example, a doped epitaxialsemiconductor layer can be grown on substrate 305, from which firstsource/drain interconnection lines YS1, YS2, . . . , YSN are formed.Alternatively, an undoped epitaxial semiconductor layer can be grown onsubstrate 305, and dopants then introduced by ion-implantation ordiffusion to obtain the first source/drain interconnection lines YS1,YS2, . . . , YSN of the desired conductivity.

Each pillar 300 is outwardly formed from substrate 305, and isillustrated in FIG. 3 as extending vertically upward from substrate 305.Each pillar 300 has a top region that is separated from substrate 305 byfour surrounding side regions. A floating gate 325 is formedsubstantially adjacent to each side surface of pillar 300, and separatedtherefrom by a gate dielectric 330, such that there are four floatinggates 325 per pillar 300, though FIG. 3 omits some of the floating gates325 for clarity of illustration. Each floating gate 325 has acorresponding substantially adjacent control gate 335, from which it isseparated by an intergate dielectric 340. Except at the periphery ofarray 105, each control gate 335 is interposed between two approximatelyadjacent pillars 300 and shared by two floating gate transistors 200,each of these floating gate transistors 200 having portions in one ofthe two approximately adjacent pillars 300.

Also interposed between approximately adjacent pillars 300, except atthe periphery of array 105, are first gate line YG1, YG2, . . . , YGNthat are substantially parallel to each other in the first direction,e.g. the Y-direction. Each of the first gate lines YG1, YG2, . . . , YGNinterconnects ones of the control gates 335. For example, first gateline YG1 electrically interconnects control gates 335 of floating gatetransistors 200 in cells 205AA, 205BA, . . . , 205BN. In the embodimentof FIG. 3, the first gate lines YG1, YG2, . . . , YGN are disposed atleast partially within substrate 305, as described below.

Also interposed between approximately adjacent pillars 300, except atthe periphery of array 105, are second gate lines XG1, XG2, . . . , XGNthat are substantially parallel to each other in the second direction,e.g. the X-direction. Each of the second gate lines XG1, XG2, . . . ,XGN interconnects ones of the control gates 335. For example, secondgate line XG2 electrically interconnects control gates 335 of floatinggate transistors 200, in which the control gates are shared betweenpairs of cells 205, e.g. 205AA and 205BA, 205AB and 205BB . . . , 205ANand 205BN. In the embodiment of FIG. 3, the second gate lines XG1, XG2,. . . , XGN are disposed above substrate 305, as described below.

Drain regions 315 of the pillars 300 are interconnected by data linesXD1, XD2, . . . , XDN that are substantially parallel to each other inthe second direction, e.g. the X-direction. FIG. 3 illustrates, by wayof example, data lines XD1 and XD2, which are shown schematically forclarity. However, it is understood that data lines XD1, XD2, . . . , XDNcomprise metal or other interconnection lines that are isolated from theunderlying topology, e.g. pillars 300, floating gates 325, control gates335, first gate lines YG1, YG2, . . . , YGN, and second gate lines XG1,XG2, . . . , XGN, by an insulating layer through which contact holes areetched to access the drain regions 315 of the pillars 300.

FIG. 4 is a plan view, looking toward the working surface of substrate305, illustrating generally by way of example one embodiment of one ofcells 205 of four floating gate transistors 200, such as cell 205BB. InFIG. 4, each of the four floating gates 325 is adjacent to one side ofpillar 300, and separated therefrom by gate dielectric 330. Each controlgate 335 is separated from a corresponding floating gate 325 by anintergate dielectric 340, and is integrally formed together with one ofthe first gate lines YG1, YG2, . . . , YGN or second gate lines XG1,XG2, . . . , XGN. The control gates 335 that are integrally formedtogether with ones of the first gate lines YG1, YG2, . . . , YGNprotrude upwardly therefrom such that an overlap capacitance is createdwith floating gates 325 that are disposed on either side thereof.

The center-to-center spacing (“pitch”) between adjacent first gate linesYG1, YG2, . . . , YGN, such as between YG2 and YG3, or between adjacentsecond gate lines XG1, XG2, . . . , XGN, such as between XG2 and XG3, istwice the minimum lithographic feature size F. Since four floating gatetransistors 200 are contained within a cell 205 having an area of 4F²,an area of only F² is needed per bit of data. In another embodiment,multiple charge states (more than two) are used to obtaincorrespondingly higher data storage densities, such that an area of lessthan F² is needed per bit of data, since more than one bit of data canbe stored on a single floating gate transistor 200. In one embodiment,four charge states are used to store two bits of data per floating gatetransistor 200, corresponding to eight bits of data per memory cell 205.One example of using more than two charge states to store more than onebit of data per transistor is set forth an article by T.-S. Jung et al.,entitled “A 117-mm² 3.3-V Only 128-Mb Multilevel NAND Flash Memory ForMass Storage Applications,” IEEE J. Solid-State Circuits, Vol. 31, No.11, November 1996. In a further embodiment, a continuum of charge statesis used to store analog data in array 105.

In one embodiment, programming of one of the floating gate transistors200 is by hot electron injection. For example, a voltage ofapproximately 10 volts is provided, such as by one of Y gate decoder 110or X gate decoder 115, through a particular one of the first gate linesYG1, YG2, . . . , YGN or second gate lines XG1, XG2, . . . , XGN to aparticular control gate 335. A resulting inversion region (channel) isformed in the body region 320 at the surface that is approximatelyadjacent to the particular one of the first gate lines YG1, YG2, . . . ,YGN or second gate lines XG1, XG2, . . . , XGN. A voltage ofapproximately 5 Volts is provided, such as by X source/drain decoder125, through a particular one of data lines XD1, XD2, . . . , XDN to aparticular drain region 315. A voltage of approximately 0 Volts isprovided, such as by Y source/drain decoder 120, through a particularone of first source/drain interconnection lines YS1, YS2, . . . , YSN,to the particular source region 310 of the floating gate transistor 200.Electrons are injected onto the floating gate 325 interposed between thecontrol gate 335 and the pillar 300 in which the particular drain region315 is disposed. The exact value of the voltages provided to theparticular control gate 335 and drain region 315 will depend on thephysical dimension of the floating gate transistor 200, including thethickness of the gate dielectric 330, the thickness of the intergatedielectric 340, and the separation between source region 310 and drainregion 315. Alternatively, if higher voltages are provided to controlgate 335, and the gate dielectric 330 and intergate dielectric 340 aremade thinner, the floating gate transistor 200 may be programmed insteadby Fowler-Nordheim tunneling of electrons h m the body region 320,source region 310, or drain region 315.

Addressing a particular memory cell 205 for reading data includesselecting a particular one of data lines XD1, XD2, . . . , XDN and alsoselecting a particular one of first source/drain interconnection linesYS1, YS2, . . . , YSN. Addressing a particular floating gate transistor200 within the particular memory cell 205 for reading data furtherincludes selecting a particular one of first gate lines YG1, YG2, . . ., YGN or second gate lines XG1, XG2, . . . , XGN.

In one embodiment, reading data stored on a particular floating gatetransistor 200 includes providing a voltage of approximately 5 volts,such as by one of Y gate decoder 110 or X gate decoder 115, through aparticular one of the first gate lines YG1, YG2, . . . , YGN or secondgate lines XG1, XG2, . . . , XGN to the particular control gate 335 ofthe floating gate transistor 200. A voltage of approximately 0 Volts isprovided, such as by Y source/drain decoder 120, through a particularone of first source/drain interconnection lines YS1, YS2, . . . , YSN,to the particular source region 310 of the particular floating gatetransistor 200. A particular one of data lines XD1, D2 . . . , XDN thatis switchably coupled to the drab region 315 of the floating gatetransistor 200 is precharged to a positive voltage by a sense amplifierin X source/drain decoder 125, then coupled to the drain region 315 todetermine the conductivity state of the floating gate transistor 200between its source region 310 and drain region 315.

If there are no electrons stored on the floating gate 325, the floatinggate transistor 200 will conduct between its source region 310 and drainregion 315, decreasing the voltage of the particular one of data linesXD1, XD2, . . . , XDN toward that voltage of its source region 310, e.g.toward a “low” binary logic level of approximately 0 Volts. If there areelectrons stored on the floating gate 325, the floating gate transistor200 will not conduct between its source region 310 and drain region 315.As a result, the sense amplifier will tend to increase the voltage ofthe particular one of data lines XD1, XD2, . . . , XDN toward a positivevoltage, e.g. toward a “high” binary logic voltage level.

In one embodiment, erasure of floating gate transistors 200 includesproviding an erasure voltage difference of approximately between −10 and−12 Volts from a source region 310 to a corresponding control gate 335.For example, a voltage of approximately 0 Volts is provided, such as byY source/drain decoder 120, to source regions 310 of floating gatetransistors 200 that are interconnected by one or several firstsource/drain interconnection lines YS1, YS2, . . . , YSN. A voltage ofapproximately between −10 and −12 Volts is provided, such as by one of Ygate decoder 110 or X gate decoder 115, through a corresponding one orseveral of the first gate lines YG1, YG2, . . . , YGN or second gatelines XG1, XG2, . . . , XGN to the control gates 335 of the floatinggate transistors 200 to be erased. As a result of the negative voltageapplied to the control gates 335, electrons are removed from thecorresponding floating gates 325 by Fowler-Nordheim tunneling, therebyerasing the data from ones of the floating gate transistors 200. Inanother example, a voltage of approximately between −5 and −6 Volts isapplied to the control gates 335 and a voltage of approximately between+5 and +6 Volts is applied to the source regions 310 in order to obtainthe erasure voltage difference of approximately between −10 and −12Volts from a source region 310 to a corresponding control gate 335. Theexact value of the erasure voltage difference will vary depending uponthe physical dimensions of the floating gate transistor 200 and thethicknesses of gate dielectric 330 and intergate dielectric 340.

In one embodiment, the entire array 105 of floating gate transistors 200is simultaneously erased by applying approximately between −10 and −12Volts to each of first gate lines YG1, YG2, . . . , YGN and second gatelines XG1, XG2, . . . , XGN, and also applying 0 Volts to each of firstsource/drain interconnection lines YS1, YS2, . . . , YSN. In anotherembodiment, one or more sectors of array 105 are simultaneously erasedby selectively applying approximately between −10 and −12 Volts to oneor more of first gate lines YG1, YG2, . . . , YGN or second gate linesXG1, XG2, . . . , XGN, and also applying 0 Volts to one or more of firstsource/drain interconnection lines YS1, YS2, . . . , YSN.

FIGS. 5-20 illustrate generally one embodiment of a method of formingmemory array 105. In this embodiment, the array 105 is formed using bulksilicon processing techniques and is described, by way of example, withrespect to a particular technology having a minimum feature size F,which is also sometimes referred to as a critical dimension (CD), of 0.4microns. However, the process steps described below can be scaledaccordingly for other minimum feature sizes without departing from thescope of the invention.

In FIG. 5, a P-silicon starting material is used for substrate 305. Afirst source/drain layer 500, of approximate thickness between 0.2microns and 0.5 microns, is formed at a working surface of substrate305. In one embodiment, first source/drain layer 500 is N+ siliconformed by ion-implantation of donor dopants into substrate 305. Inanother embodiment, first source/drain layer 500 is N+ silicon formed byepitaxial growth of silicon upon substrate 305. On the firstsource/drain layer 500, a semiconductor epitaxial layer 505, such asP-silicon of 0.6 micron approximate thickness, is formed, such as byepitaxial growth. A second source/drain layer 510, such as N+ silicon of150 nanometer approximate thickness, is formed at a surface of theepitaxial layer 505, such as by ion-implantation of donor dopants intoP-epitaxial layer 505 or by epitaxial growth of N+ silicon onP-epitaxial layer 505. A thin layer of silicon dioxide (SiO₂), referredto as pad oxide 515, is deposited on the second source/drain layer 510.Pad oxide 515 has a thickness of approximately 10 nanometers. A layer ofsilicon nitride (Si₃N₄), referred to as pad nitride 520, is deposited onthe pad oxide 515. Pad nitride 520 has a thickness of approximately 200nanometers.

In FIG. 6, photoresist masking and selective etching techniques are usedto form, in the first direction (e.g., the Y direction, which isperpendicular to the plane of the drawing of FIG. 6), a plurality ofsubstantially parallel first troughs 600 that extend through the padnitride 520, pad oxide 515, second source/drain layer 510, theunderlying portion of epitaxial layer 505, and at least partially intofirst source/drain layer 500. The photoresist is then removed.

In FIG. 7, a thin silicon nitride oxidation barrier layer 700 isdeposited by chemical vapor deposition (CVD) to protect againstoxidation of sidewalls of first troughs 600. Barrier layer 700 isanisotropically etched to expose bottom portions of first troughs 600. Abottom insulation layer 705 of silicon dioxide is formed on the bottomsof first troughs 600 by thermal oxidation of the exposed bottom portionsof first troughs 600.

In FIG. 8, barrier layer 700 is stripped from the sidewalls of the firsttroughs 600, such as by a brief phosphoric acid etch, which is timed toexpose the sidewalls of the first troughs 600 but which avoidssignificant removal of the pad nitride 520. A first gate dielectriclayer 800 such as, for example, silicon dioxide of thicknessapproximately between 5 nanometers and 10 nanometers (sometimes referredto as “tunnel oxide”), is formed substantially adjacent to the exposedsidewalls of the first troughs 600. A first conductive layer 805, suchas N+ doped polysilicon, is formed in the first troughs 600, such as byCVD, to fill the first troughs 600. The first conductive layer 805 isplanarized, such as by chemical mechanical polishing (CMP) or othersuitable planarization technique.

In FIG. 9, the first conductive layer 805 is etched back in the firsttroughs 600 to approximately 100 nanometers below the silicon surface,which is defined by the interface between the second source/drain layer510 and the pad oxide 515 layer. A first spacer layer, such as siliconnitride of an approximate thickness of 7 nanometers, is deposited by CVDand anisotropically etched by reactive ion etching (RIE) to leavenitride first spacers 900 along the sidewalls of the first troughs 600.A second spacer layer, such as silicon dioxide of an approximatethickness of 90 nanometers, is deposited by CVD and anisotropicallyetched by RIE to leave second spacers 905 along the sidewalls of thefirst troughs 600.

In FIG. 10, a portion of the first conductive layer 805 in first troughs600 between second spacers 905 is removed, such as by using spacers 905as a mask while etching down to bottom insulation layer 705, therebyforming from the first conductive layer 805 floating gate regions 1000along the sidewalls of the first troughs 600. A thin oxidation barrierlayer 1005, such as silicon nitride of approximate thickness of 5nanometers, is deposited by CVD. Barrier layer 1005 is removed from thebottom insulation layer 705 in first troughs 600 by anisotropic etching.The remaining portions of barrier layer 1005 protect the floating gateregions 1000 during subsequent processing described below.

In FIG. 11, a portion of the bottom insulation layer 705 is removed,exposing a portion of the underlying substrate 305, by an anisotropicetch that is timed to leave enough of second spacers 905 to protectfloating gate regions 1000 during a subsequent etch of substrate 305. Aportion of substrate 305 that underlies a portion of first troughs 600between the floating gate regions 1000 is removed by selectivelyanisotropically etching the substrate 305 to a depth sufficient to carrythe first gate lines YG1, YG2, . . . , YGN. A first trough insulationlayer 1100 is formed on sidewall and bottom regions of the etchedportions of substrate 305 underlying the first troughs 600. Barrierlayer 1005 is removed to expose the floating gate regions 1000 in firsttroughs 600, such as by wet etching.

The first intergate dielectric 340, having an approximate thicknessbetween 7 nanometers and 15 nanometers, is formed on the exposedportions of floating gate regions 1000. In one embodiment, a silicondioxide intergate dielectric 340 is formed by thermal oxidation of thefloating gate regions 1000. In another embodiment, an oxynitrideintergate dielectric 340 is formed on the floating gate regions 1000 byCVD.

First gate lines YG1, YG2, . . . , YGN are formed in the etched portionsof substrate 305 underlying the first troughs 600 between opposingfloating gate regions 1000 in the first troughs 600. First gate linesYG1, YG2, . . . , YGN are insulated from substrate 305 by first troughinsulation layer 1100. Control gates 335 are formed in the first troughs600 between opposing floating gate regions 1000, and separated therefromby the first intergate dielectric 340. In one embodiment, first gatelines YG1, YG2, . . . , YGN and control gates 335 are formed together bydepositing N+ polysilicon to fill first troughs 600, and etching backthe deposited N+ polysilicon approximately to the top portion of thefloating gate regions 1000.

In FIG. 12, a cap layer 1200 is formed, such as by CVD of silicondioxide, and then planarized, such as by CMP, such that the top surfaceof cap layer 1200 is substantially even with the top surface of padnitride 520. A masking layer 1205 is formed, such as silicon nitridedeposited by CVD to an approximate thickness of 100 nanometers. Anothermasking layer 1210 is also formed, such as polysilicon deposited by CVDto an approximate thickness of 100 nanometers. A photoresist layer 1215is formed on masking layer 1210.

FIG. 13 is a perspective view, illustrating the selective etching, in asecond direction (X-direction) that is substantially orthogonal to thefirst direction (Y-direction), of a plurality of substantially parallelsecond troughs 1300, as described below. Forming second troughs 1300includes selectively etching masking layer 1210 and underlying maskinglayer 1205, such that portions of cap layer 1200 in the second troughs1300 are exposed. With photoresist layer 1215 still in place, anonselective dry etch is used to simultaneously remove exposed silicondioxide and polysilicon in intersecting portions of first troughs 600and second troughs 1300, including the removing of: portions of caplayer 1200, gate dielectric 800, floating gate regions 1000, intergatedielectric 340, and the control gate 335 portions of first gate linesYG1, YG2, . . . , YGN. The nonselective dry etch removal proceeds atleast to the depth of the interface between floating gate regions 1000and underlying bottom insulation layer 705, thereby separating floatinggate regions 1000 into the isolated floating gates 325. During thenonselective dry etch, the regions between first troughs 600 areprotected by the pad nitride 520 and the regions between second troughs1300 are protected by selectively patterned photoresist layer 1215.

In the plan view of FIG. 14, the photoresist layer 1215 has been removedby conventional photoresist stripping techniques, thereby exposing theunderlying. selectively patterned polysilicon masking layer 1210. Aninsulating layer 1400, such as silicon dioxide deposited by CVD, isformed everywhere on the topography of the working surface of substrate305, thereby filling the nonselectively dry-etched intersections of thefirst troughs 600 and second troughs 1300. The insulating layer 1400 isthen planarized, such as by CMP, and recess etched to a depth that isslightly above the interface between second source-drain layer 510 andpad oxide 515, thereby leaving behind recessed portions of insulatinglayer 1400 in the nonselectively dry-etched intersections of the firsttroughs 600 and second troughs 1300, as illustrated in FIG. 14.

In the plan view of FIG. 15, the exposed portions of pad nitride 520(e.g., between first troughs 600 and within second troughs 1300) areremoved by a selective etch of silicon nitride, thereby exposingunderlying portions of pad oxide 515. The exposed portions of pad oxide515 (e.g., between first troughs 600 and within second troughs 1300) areremoved by dipping into a wet etchant, which is timed to remove theexposed portions of pad oxide 515, but to leave most of the remainingportions of the thicker silicon dioxide insulating layer 1400 intact.The removing of portions of pad oxide 515 exposes the secondsource/drain layer 510 portion of the underlying silicon epitaxial layer505. The exposed portions of silicon epitaxial layer 505 (e.g., betweenfirst troughs 600 and within second troughs 1300) are removed by aselective etching that is preferential to silicon over silicon dioxide,thereby forming recesses 1500 in second troughs 1300 between firsttroughs 600. Recesses 1500, which are considered to be part of secondtroughs 1300, are etched through epitaxial layer 505 and at leastpartially into first source/drain layer 500. Etching recesses 1500 alsoremoves the remaining portions of polysilicon masking layer 1210,thereby exposing underlying silicon nitride masking layer 1205, asillustrated in FIG. 15.

FIG. 16 is a cross-sectional view in the direction of second troughs1300 (e.g. such that the X-direction is orthogonal to the plane of theillustration of FIG. 16). as indicated by the cut line 16-16 in FIG. 15.In FIG. 16, a thin silicon nitride oxidation barrier layer 1600 isdeposited by CVD to protect against oxidation of sidewalls of secondtroughs 1300. Barrier layer 1600 is anisotropically etched to exposebottom portions of second troughs 1300. A bottom insulation layer 1605of silicon dioxide is formed on the bottoms of second troughs 1300, suchas silicon dioxide of approximate thickness of 50 nanometers formed bythermal oxidation of the exposed bottom portions of second troughs 1300.

In FIG. 17, barrier layer 1600 is stripped from the sidewalls of thesecond troughs 1300, such as by a brief phosphoric acid etch, which istimed to expose the sidewalls of the second troughs 1300 but whichavoids significant removal of the silicon nitride masking layer 1205. Asecond gate dielectric layer 1700, such as silicon dioxide of thicknessapproximately between 5 nanometers and 10 nanometers (sometimes referredto as “tunnel oxide”), is formed substantially adjacent to the exposedsidewalls of the second troughs 1300. A second conductive layer 1705,such as N+ doped polysilicon, is formed in the second troughs 1300, suchby CVP, to fill the second troughs 1300. The second conductive layer1705 is planarized such as by chemical mechanical polishing (CMP) orother suitable planarization technique.

In FIG. 18, the second conductive layer 1705 is etched back in thesecond troughs 1300 to approximately at or slightly above the level ofthe silicon surface, which is defined by the interface between thesecond source/drain layer 510 and the pad oxide 515 layer. Thus, in thesecond troughs 1300, the top surface of the second conductive layer 1705is approximately even with the top surface of the recessed portions ofinsulating layer 1400. A spacer layer, such as silicon nitride of anapproximate thickness of 100 nanometers, is deposited by CVD andanisotropically etched by reactive ion etching (RTE) to leave nitridethird spacers 1800, along the sidewalls of the second troughs 1300, e.g.on the etched back portions of the second conductive layer 1705 and onthe recessed portions of insulating layer 1400, and against the secondgate dielectric 1700.

In the perspective view of FIG. 19; third spacers 1800 are used as amask for the anisotropic etching of the etched back portions ofpolysilicon second conductive layer 1705 together with the recessedportions of silicon dioxide insulating layer 1400. By first utilizing anetchant to remove silicon dioxide, the second troughs 1300 are etched ininsulating layer 1400 to a depth sufficient to carry a second gate lineX1, X2, . . . , XN, but not so great as to expose the first gate linesY1, Y2, . . . , YN underlying the recessed portions of silicon dioxideinsulating layer 1400 in second troughs 1300. Then, the anisotropic etchis continued using a selective etchant to remove polysilicon but notsilicon dioxide until the bottom insulation layer 1605 is exposed,thereby forming from the second conductive layer 1705 separate floatinggates 325 along the sidewalls of the second troughs 1300.

In the perspective view of FIG. 20, a second intergate dielectric 2000is formed in the second troughs 1300, such that the second intergatedielectric 2000 has an approximate thickness between 7 nanometers and 15nanometers and being formed by thermal growth of silicon dioxide ordeposition of oxynitride by CVD. Control gates 335 are formed betweenopposing floating gates 325 in the second troughs 1300 and separatedtherefrom by the second intergate dielectric 2000. The control gates 335in second troughs 1300 are formed together with the second gate linesX1, X2, . . . , XN in second troughs 1300 by a single deposition of N+doped polysilicon that fills second troughs 1300 and is planarized, suchas by CMP. Phosphoric acid is used to remove the remaining siliconnitride, such as third spacers 1800, masking layer 1205, and pad nitride520, leaving the structure illustrated in FIG. 20. An insulator such assilicon dioxide is then deposited, and subsequent processing followsconventional techniques for forming contact holes, terminal metal, andinter level insulator steps to complete wiring of the cells 205 andother circuits of memory 100.

Though FIGS. 5-20 illustrate generally one embodiment of forming thememory array 105 using bulk silicon processing techniques, in anotherembodiment a semiconductor-on-insulator (SOI) substrate is formed fromsubstrate 305. In one such embodiment, a P-silicon starting material isused for substrate 305, and processing proceeds similarly to the bulksemiconductor embodiment described in FIG. 5-7. However, after thebarrier layer 700 is formed in FIG. 7, an isotropic chemical etch isused to fully undercut the semiconductor regions separating the firsttroughs 600, and a subsequent oxidation step is used to fill in theevacuated regions formed by the undercutting. As a result, an insulatoris formed on the bottoms of first troughs 600, bars of SOI are formedbetween first troughs 600, and the topography on the working surface ofsubstrate 305 is separated from substrate 305 by an insulating layer2100 illustrated in the perspective view of FIG. 21.

Thus, in the above described Figures, substrate 305 is understood toinclude bulk semiconductor as well as SOI embodiments in which thesemiconductor integrated circuits formed on the surface of substrate 305are isolated from each other and an underlying semiconductor portion ofsubstrate 305 by an insulating layer.

One such method of forming bars of SOI is described in the Noble U.S.patent application Ser. No. 08/745,708 which is assigned to the assigneeof the present application and which is herein incorporated byreference. Another such method of forming regions of SOI is described inthe Forbes U.S. patent application Ser. No. 08/706,230, which isassigned to the assignee of the present application and which is hereinincorporated by reference.

In an SOI embodiment of the present invention, processing of firsttroughs 600 to carry the first gate lines YG1, YG2, . . . , YGN variesslightly from the bulk semiconductor embodiment described with respectto FIGS. 10 and 11. A barrier layer 1005 need not be formed to protectthe floating gate regions 1000. A portion of the substrate 305 thatunderlies a portion of the first troughs 600 between the floating gateregions 1000 is removed by selectively anisotropically etching thesilicon dioxide insulator portion of substrate 305 to a depth sufficientto carry the first gate lines YG1, YG2, . . . , YGN. A portion of theresulting structure of array 105 is illustrated in the perspective viewof FIG. 21, which includes an insulating layer 2100 portion of substrate305, as described above.

Thus, the present invention provides an ultra high density flash EEPROMhaving increased nonvolatile storage capacity. If a floating gatetransistor 200 is used to store a single bit of data, an area of only F²is needed per bit of data. If multiple charge states (more than two) areused, an area of less than F² is needed per bit of data. The increasedstorage capacity of the ultra high density flash EEPROM is particularlyadvantageous in replacing hard disk drive data storage in computersystems. In such an application, the delicate mechanical componentsincluded in the hard disk drive are replaced by rugged, small, anddurable solid-state ultra high density flash EEPROM packages. The ultrahigh density flash EEPROMs provide improved performance, extendedrewrite cycles, increased reliability, lower power consumption, andimproved portability.

It is to be understood that the above description is intended to beillustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reviewing the abovedescription. For example, though the memory cells 205 have beendescribed with respect to a particular embodiment having four floatinggate transistors 200 per pillar 300, a different number of floating gatetransistors per pillar could also be used. It is also understood thatthe above structures and methods, which have been described with respectto EEPROM memory devices having floating gate transistors 200, are alsoapplicable to dynamic random access memories (DRAMS) or other integratedcircuits using vertically oriented field-effect transistors (s) that donot have floating gates. Thus, the scope of the invention is not limitedto the particular embodiments shown and described herein.

1. A method of forming a memory array on a substrate, comprising:forming a first source/drain layer at a surface of the substrate;forming a semiconductor epitaxial layer on the first source/drain layer;forming a second source/drain layer at a surface of the epitaxial layer;etching, in a first direction, a plurality of substantially parallelfirst troughs in the epitaxial layer; forming a first gate dielectriclayer substantially adjacent to sidewall regions of the first troughs;forming a first conductive layer in the first troughs; removing aportion of the first conductive layer in the first troughs such thatfloating gate regions are formed along the sidewall regions therein andseparated from the sidewall regions by the first gate dielectric layer;etching a portion of the substrate underlying a portion of the firsttroughs between the floating gate regions; forming a first intergatedielectric layer on exposed portions of the floating gate regions in thefirst troughs; forming first gate lines in the underlying etched portionof the substrate between opposing floating gate regions in the firsttroughs; and forming control gate regions in the first troughs betweenopposing floating gate regions and separated therefrom by the firstintergate dielectric layer.
 2. The method of claim 1, furthercomprising: etching, in a second direction that is substantiallyorthogonal to the first direction, a plurality of substantially parallelsecond troughs in the epitaxial layer; forming a second gate dielectriclayer substantially adjacent to sidewall regions of the second troughs;forming a second conductive layer in the second troughs; removing aportion of the second conductive layer in the second troughs such thatfloating gate regions are formed along the sidewall regions therein andseparated from the sidewall regions by the second gate dielectric layer;forming a second intergate dielectric layer on exposed portions of thefloating gate regions in the second troughs; and forming control gateregions and second gate lines between opposing floating gate regions inthe second troughs by the second intergate dielectric layer.
 3. Themethod of claim 1, wherein the substrate further comprises a bulksemiconductor.
 4. The method of claim 1, wherein the substrate furthercomprises a semiconductor on insulator portion.
 5. The method of claim1, further comprising: forming an insulating layer undercuttingsemiconductor regions between the first troughs.
 6. The method of claim2, further comprising: forming a thin silicon nitride oxidation barrierlayer by chemical vapor deposition on the sidewall regions of the secondtroughs; anisotropically etching the thin silicon nitride oxidationbarrier layer to expose bottom portions of the second troughs; forming abottom insulation layer on the bottom portions of the second troughs bythermal oxidation; and stripping the thin silicon nitride oxidationbarrier layer from the sidewall regions of the second troughs by a briefphosphoric acid etch.
 7. A method, comprising: forming a firstsource/drain layer at a surface of a substrate; forming a secondsource/drain layer at a surface of an epitaxial layer, the epitaxiallayer being formed on the first source/drain layer and comprisingP-silicon; forming a thin layer of silicon dioxide on the secondsource/drain layer; forming a layer of silicon nitride on the thin layerof silicon dioxide; etching a plurality of substantially paralleltroughs in the epitaxial layer; forming at least two floating gateregions along sidewall regions of the troughs and separated from thesidewall regions by a gate dielectric layer; forming gate lines betweenopposing floating gate regions in the troughs; and forming control gateregions in the troughs between opposing floating gate regions andseparated therefrom by an intergate dielectric layer.
 8. The method ofclaim 7, wherein forming the first source/drain layer further comprisesforming the first source/drain layer with an approximate thicknessranging between 0.2 microns and 0.5 microns.
 9. The method of claim 7,wherein forming the thin layer of silicon dioxide further comprisesforming the thin layer of silicon dioxide with an approximate thicknessof 10 nanometers.
 10. A method, comprising: forming a first source/drainlayer at a surface of a substrate, the first source/drain comprising N+silicon formed by epitaxial growth of silicon upon the substrate;forming a semiconductor epitaxial layer on the first source/drain layer;forming a second source/drain layer at a surface of the epitaxial layerby ion implantation, the second source/drain layer comprising N+ siliconand having an approximate thickness of 150 nanometers; forming a thinlayer of silicon dioxide on the second source/drain layer, the thinlayer of silicon dioxide having an approximate thickness of 10nanometers; forming a layer of silicon nitride on the thin layer ofsilicon dioxide, the layer of silicon nitride having an approximatethickness of 200 nanometers; etching a plurality of substantiallyparallel troughs in the epitaxial layer; forming at least two floatinggate regions along sidewall regions of the troughs and separated fromthe sidewall regions by a gate dielectric layer; forming gate linesbetween opposing floating gate regions in the troughs; and formingcontrol gate regions in the troughs between opposing floating gateregions and separated therefrom by an intergate dielectric layer. 11.The method of claim 10, wherein forming the first source/drain layerfurther comprises forming the first source/drain layer with anapproximate thickness ranging between 0.2 microns and 0.5 microns. 12.The method of claim 10, wherein forming at least two floating gateregions further comprises forming the at least two floating gate regionsalong the sidewall regions of the troughs and separated from thesidewall regions by the gate dielectric layer, the gate dielectric layerhaving an approximate thickness that ranges between 5 nanometers and 10nanometers.
 13. A method, comprising: forming a first source/drain layerat a surface of a substrate, the substrate comprised of asemiconductor-on-insulator portion, and the a first source/drain layercomprising N+ silicon formed by ion implantation of donor dopants intothe substrate; forming a semiconductor epitaxial layer on the firstsource/drain layer, the semiconductor epitaxial layer comprisingP-silicon and having an approximate thickness of 0.6 microns; forming asecond source/drain layer at a surface of the epitaxial layer by ionimplantation, the second source/drain layer comprising N+silicon andhaving an approximate thickness of 150 nanometers; forming a thin layerof silicon dioxide on the second source/drain layer; forming a layer ofsilicon nitride on the thin layer of silicon dioxide; etching aplurality of substantially parallel troughs in the epitaxial layer;forming at least two floating gate regions along sidewall regions of thetroughs and separated from the sidewall regions by a gate dielectriclayer; forming gate lines between opposing floating gate regions in thetroughs; and forming control gate regions in the troughs betweenopposing floating gate regions and separated therefrom by an intergatedielectric layer.
 14. The method of claim 13, further comprising:forming a conductive layer in the troughs.
 15. The method of claim 14,further comprising: removing a portion of the conductive layer in thetroughs; and etching a portion of the substrate underlying a portion ofthe troughs between floating gate regions.
 16. The method, comprising:forming a first source/drain layer at a surface of a substrate, thefirst source/drain comprising N+silicon formed by ion implantation ofdonor dopants into the substrate; forming a second source/drain layer ata surface of an epitaxial layer, the epitaxial layer being formed on thefirst source/drain layer and comprising P-silicon; forming a thin layerof silicon dioxide on the second source/drain layer; forming a layer ofsilicon nitride on the thin layer of silicon dioxide; etching aplurality of substantially parallel troughs in the epitaxial layer;forming an insulating layer undercutting semiconductor regions betweenthe troughs; forming at least two floating gate regions along sidewallregions of the troughs and separated from the sidewall regions by a gatedielectric layer; forming gate lines between opposing floating gateregions in the troughs; and forming control gate regions in the troughsbetween opposing floating gate regions and separated therefrom by anintergate dielectric layer.
 17. The method of claim 16, wherein formingat least two floating gate regions further comprises forming at leasttwo floating gate regions along the sidewall regions of the troughs andseparated from the sidewall regions by the gate dielectric layer, thegate dielectric layer having an approximate thickness that rangesbetween 5 nanometers and 10 nanometers.
 18. The method of claim 16,wherein forming control gate regions further comprises forming controlgate regions in the troughs between opposing floating gate regions andseparated therefrom by an intergate dielectric layer, the intergatedielectric layer having an approximate thickness that ranges between 7nanometers and 15 nanometers.
 19. A method, comprising: forming a firstsource/drain layer at a surface of a substrate; forming a secondsource/drain layer at a surface of an epitaxial layer, the epitaxiallayer being formed on the first source/drain layer; etching a pluralityof substantially parallel troughs in the epitaxial layer; forming a thinsilicon nitride oxidation barrier layer by chemical vapor deposition onsidewall regions of the troughs; anisotropically etching the thinsilicon nitride oxidation barrier layer to expose bottom portions of thetroughs; forming a bottom insulation layer on the bottom portions of thetroughs by thermal oxidation; forming at least two floating gate regionsalong sidewall regions of the troughs and separated from the sidewallregions by a gate dielectric layer; and forming control gate regions inthe troughs between opposing floating gate regions and separatedtherefrom by an intergate dielectric layer.
 20. The method of claim 19,further comprising: planarizing the first conductive layer using achemical mechanical polish.
 21. The method of claim 19, furthercomprising: stripping the thin silicon nitride oxidation barrier layerfrom the sidewall regions by a phosphoric acid etch.
 22. The method ofclaim 19, wherein forming a first source/drain layer further comprises:forming the first source/drain layer at the surface of the substrate,wherein the substrate is a bulk semiconductor.
 23. A method, comprising:forming a first source/drain layer at a surface of a substrate; forminga second source/drain layer at a surface of an epitaxial layer; etching,in a first direction, a plurality of substantially parallel firsttroughs in the epitaxial layer; forming a first bottom insulation layeron bottom portions of the first troughs by thermal oxidation; formingfirst floating gate regions along sidewall regions of the first troughsand separated from the sidewall regions by a first gate dielectriclayer; forming first control gate regions between opposing firstfloating gate regions, the first control gate regions being separatedfrom the first floating gate regions by a first intergate dielectriclayer; etching, in a second direction substantially orthogonal to thefirst direction, a plurality of substantially parallel second troughs inthe epitaxial layer; forming second floating gate regions along sidewallregions of the second troughs and separated from the sidewall regions bya second gate dielectric layer; and forming second control gate regionsin the troughs between opposing second floating gate regions, the secondcontrol gate regions being separated from the second floating gateregions by a second intergate dielectric layer.
 24. The method of claim23, further comprising: forming a second bottom insulation layer onbottom portions of the second troughs by thermal oxidation.
 25. Themethod of claim 23, further comprising: forming the second dielectriclayer by deposition of oxynitride using chemical vapor deposition. 26.The method of claim 23, wherein forming first floating gate regionsfurther comprises: forming the first floating gate regions along thesidewall regions of the first troughs and separated from the sidewallregions by the first gate dielectric layer, the first gate dielectriclayer having an approximate thickness that ranges between 5 nanometersand 10 nanometers.
 27. The method of claim 23, wherein forming secondcontrol gate regions further comprises: forming the second control gateregions along the sidewall regions of the second troughs and separatedfrom the sidewall regions by the second gate dielectric layer, thesecond gate dielectric layer having an approximate thickness that rangesbetween 5 nanometers and 10 nanometers.
 28. A method, comprising:forming a first source/drain layer at a surface of a substrate; forminga second source/drain layer at a surface of an epitaxial layer; etching,in a first direction, a plurality of substantially parallel firsttroughs in the epitaxial layer; forming a first dielectric layer alongsidewall regions of the first troughs; forming first floating gateregions along sidewall regions of the first troughs and separated fromthe sidewall regions by the first gate dielectric layer, the firstfloating gate regions including a first conductive layer of N+ dopedpolysilicon; forming first control gate regions between opposing firstfloating gate regions, the first control gate regions being separatedfrom the first floating gate regions by a first intergate dielectriclayer, and the first control gate regions including N+ dopedpolysilicon; forming first gate lines in the first troughs betweenopposing first floating gate regions; etching, in a second directionsubstantially orthogonal to the first direction, a plurality ofsubstantially parallel second troughs in the epitaxial layer; removingmaterial at intersecting portions of first troughs and second troughs toseparate the first floating gate regions into first isolated floatinggates; forming a second gate dielectric layer along sidewall regions ofthe second troughs; forming second floating gate regions along thesidewall regions of the second troughs and separated from the sidewallregions by a second gate dielectric layer, the second floating gateregions including a second conductive layer of N+ doped polysilicon;forming second control gate regions between opposing second floatinggate regions, the second control gate regions being separated from thesecond floating gate regions by a second intergate dielectric layer, andthe second control gate regions including N+ doped polysilicon; andforming second gate lines in the second troughs between opposing secondfloating gate regions.
 29. A method, comprising: forming a firstsource/drain layer at a surface of a substrate; forming a secondsource/drain layer at a surface of an epitaxial layer; etching, in afirst direction, a plurality of substantially parallel first troughs inthe epitaxial layer; forming first floating gate regions along sidewallregions of the first troughs and separated from the sidewall regions bythe first gate dielectric layer, the first floating gate regionsincluding a first conductive layer of N+ doped polysilicon; formingfirst control gate regions between opposing first floating gate regions,the first control gate regions being separated from the first floatinggate regions by a first intergate dielectric layer; etching, in a seconddirection substantially orthogonal to the first direction, a pluralityof substantially parallel second troughs in the epitaxial layer; formingsecond floating gate regions along sidewall regions of the secondtroughs and separated from the sidewall regions by a second gatedielectric layer, the second floating gate regions including a secondconductive layer of N+ doped polysilicon; and forming second controlgate regions between opposing second floating gate regions, the secondcontrol gate regions being separated from the second floating gateregions by a second intergate dielectric layer.
 30. A method,comprising: forming a first source/drain layer at a surface of asubstrate; forming a second source/drain layer at a surface of anepitaxial layer; etching, in a first direction, a plurality ofsubstantially parallel first troughs in the epitaxial layer; formingfirst floating gate regions along sidewall regions of the first troughsand separated from the sidewall regions by the first gate dielectriclayer; forming first control gate regions between opposing firstfloating gate regions, the first control gate regions being separatedfrom the first floating gate regions by a first intergate dielectriclayer, and the first control gate regions including N+ dopedpolysilicon; etching, in a second direction substantially orthogonal tothe first direction, a plurality of substantially parallel secondtroughs in the epitaxial layer; forming second floating gate regionsalong sidewall regions of the second troughs and separated from thesidewall regions by a second gate dielectric layer; and forming secondcontrol gate regions between opposing second floating gate regions, thesecond control gate regions being separated from the second floatinggate regions by a second intergate dielectric layer, and the secondcontrol gate regions including N+ doped polysilicon.
 31. A method,comprising: forming a first source/drain layer at a surface of asubstrate; forming a second source/drain layer at a surface of anepitaxial layer; etching, in a first direction, a plurality ofsubstantially parallel first troughs in the epitaxial layer; formingfirst floating gate regions along sidewall regions of the first troughsand separated from the sidewall regions by a first gate dielectriclayer; forming first control gate regions between opposing firstfloating gate regions, the first control gate regions being separatedfrom the first floating gate regions by a first intergate dielectriclayer; forming first gate lines in the first troughs between opposingfirst floating gate regions; etching, in a second directionsubstantially orthogonal to the first direction, a plurality ofsubstantially parallel second troughs in the epitaxial layer; formingsecond floating gate regions along sidewall regions of the secondtroughs and separated from the sidewall regions by a second gatedielectric layer; forming second control gate regions between opposingsecond floating gate regions, the second control gate regions beingseparated from the second floating gate regions by a second intergatedielectric layer; and forming second gate lines in the second troughsbetween opposing second floating gate regions.
 32. A method, comprising:forming a first source/drain layer at a surface of a substrate; forminga second source/drain layer at a surface of an epitaxial layer; etching,in a first direction, a plurality of substantially parallel firsttroughs in the epitaxial layer; forming first floating gate regionsalong sidewall regions of the first troughs and separated from thesidewall regions by a first gate dielectric layer; forming first controlgate regions between opposing first floating gate regions, the firstcontrol gate regions being separated from the first floating gateregions by a first intergate dielectric layer, and the first controlgate regions are formed together with first gate lines by depositing N+polysilicon in the first troughs; etching, in a second directionsubstantially orthogonal to the first direction, a plurality ofsubstantially parallel second troughs in the epitaxial layer; formingsecond floating gate regions along sidewall regions of the secondtroughs and separated from the sidewall regions by a second gatedielectric layer; and forming second control gate regions betweenopposing second floating gate regions, the second control gate regionsbeing separated from the second floating gate regions by a secondintergate dielectric layer, and the second control gate regions areformed together with second gate lines by depositing N+ polysilicon inthe second troughs.
 33. A method, comprising: forming a firstsource/drain layer at a surface of a substrate; forming a secondsource/drain layer at a surface of an epitaxial layer; etching, in afirst direction, a plurality of substantially parallel first troughs inthe epitaxial layer; forming first floating gate regions along sidewallregions of the first troughs and separated from the sidewall regions bya first gate dielectric layer; forming first control gate regionsbetween opposing first floating gate regions, the first control gateregions being separated from the first floating gate regions by a firstintergate dielectric layer; etching, in a second direction substantiallyorthogonal to the first direction, a plurality of substantially parallelsecond troughs in the epitaxial layer; removing material at intersectingportions of first troughs and second troughs to separate the firstfloating gate regions into first isolated floating gates; forming secondfloating gate regions along sidewall regions of the second troughs andseparated from the sidewall regions by a second gate dielectric layer;and forming second control gate regions between opposing second floatinggate regions, the second control gate regions being separated from thesecond floating gate regions by a second intergate dielectric layer. 34.A method, comprising: forming a first source/drain layer at a surface ofa substrate; forming a second source/drain layer at a surface of anepitaxial layer; etching, in a first direction, a plurality ofsubstantially parallel first troughs in the epitaxial layer; forming afirst gate dielectric layer along sidewall regions of the first troughs;forming first floating gate regions along the sidewall regions of thefirst troughs and separated from the sidewall regions by a first gatedielectric layer; forming first control gate regions between opposingfirst floating gate regions, the first control gate regions beingseparated from the first floating gate regions by a first intergatedielectric layer; etching, in a second direction substantiallyorthogonal to the first direction, a plurality of substantially parallelsecond troughs in the epitaxial layer; forming a second gate dielectriclayer along sidewall regions of the second troughs; forming secondfloating gate regions along the sidewall regions of the second troughsand separated from the sidewall regions by the second gate dielectriclayer; and forming second control gate regions between opposing secondfloating gate regions, the second control gate regions being separatedfrom the second floating gate regions by a second intergate dielectriclayer.